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IPPS
2006
IEEE
16 years 15 days ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
LCPC
2009
Springer
15 years 11 months ago
MIMD Interpretation on a GPU
Programming heterogeneous parallel computer systems is notoriously difficult, but MIMD models have proven to be portable across multi-core processors, clusters, and massively paral...
Henry G. Dietz, B. Dalton Young
FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 10 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
ASPLOS
2006
ACM
16 years 13 days ago
Combinatorial sketching for finite programs
Sketching is a software synthesis approach where the programmer develops a partial implementation — a sketch — and a separate specification of the desired functionality. The ...
Armando Solar-Lezama, Liviu Tancau, Rastislav Bod&...
ISHPC
2000
Springer
15 years 10 months ago
Leveraging Transparent Data Distribution in OpenMP via User-Level Dynamic Page Migration
This paper describes transparent mechanisms for emulating some of the data distribution facilities offered by traditional data-parallel programming models, such as High Performance...
Dimitrios S. Nikolopoulos, Theodore S. Papatheodor...