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2009
IEEE
15 years 7 months ago
A scalable parallel H.264 decoder on the cell broadband engine architecture
The H.264 video codec provides exceptional video compression while imposing dramatic increases in computational complexity over previous standards. While exploiting parallelism in...
Michael A. Baker, Pravin Dalale, Karam S. Chatha, ...
CGO
2007
IEEE
16 years 24 days ago
Evaluating Heuristic Optimization Phase Order Search Algorithms
Program-specific or function-specific optimization phase sequences are universally accepted to achieve better overall performance than any fixed optimization phase ordering. A ...
Prasad Kulkarni, David B. Whalley, Gary S. Tyson
WORDS
2005
IEEE
16 years 21 hour ago
Experiments with WCET-Oriented Programming and the Single-Path Architecture
The single-path software/hardware architecture has been conceived with the goal to support real-time task execution with highly predictable timing. By using WCET-oriented programm...
Peter P. Puschner
DATE
2003
IEEE
180views Hardware» more  DATE 2003»
15 years 11 months ago
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibil...
Frank Gilbert, Michael J. Thul, Norbert Wehn
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
15 years 12 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...