2852 search results - page 168 / 571 » High Performance Architectures and Compilers |
169
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ICIP
1994
IEEE
16 years 7 months ago
1994
IEEE
In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been i...
172
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
166
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ISVLSI
2005
IEEE
16 years 30 min ago
2005
IEEE
The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique...
173
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ATS
2004
IEEE
15 years 10 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
170
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DAGSTUHL
1994
15 years 7 months ago
1994
Abstract. Rampart is a toolkit of protocols to facilitate the development of high-integrity services, i.e., distributed services that retain their availability and correctness desp...