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CODES
2004
IEEE
15 years 10 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
CASES
2006
ACM
15 years 10 months ago
An accurate and efficient simulation-based analysis for worst case interruption delay
This paper proposes an efficient method to analyze worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our...
Hiroshi Nakashima, Masahiro Konishi, Takashi Nakad...
CASES
2001
ACM
15 years 10 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
TSE
2008
89views more  TSE 2008»
15 years 6 months ago
WASP: Protecting Web Applications Using Positive Tainting and Syntax-Aware Evaluation
Many software systems have evolved to include a Web-based component that makes them available to the public via the Internet and can expose them to a variety of Web-based attacks. ...
William G. J. Halfond, Alessandro Orso, Pete Manol...
OOPSLA
2010
Springer
15 years 4 months ago
Instrumentation and sampling strategies for cooperative concurrency bug isolation
Fixing concurrency bugs (or crugs) is critical in modern software systems. Static analyses to find crugs such as data races and atomicity violations scale poorly, while dynamic a...
Guoliang Jin, Aditya V. Thakur, Ben Liblit, Shan L...