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HPCA
1998
IEEE
15 years 10 months ago
Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory
A key challenge in achieving high performance on software DSM systems is overcoming their relatively large communication latencies. In this paper, we consider two techniques which...
Todd C. Mowy, Charles Q. C. Chan, Adley K. W. Lo
HIPEAC
2010
Springer
15 years 8 months ago
Computer Generation of Efficient Software Viterbi Decoders
This paper presents a program generator for fast software Viterbi decoders for arbitrary convolutional codes. The input to the generator is a specification of the code and a single...
Frédéric de Mesmay, Srinivas Chellap...
ICPP
1999
IEEE
15 years 10 months ago
Coherence-Centric Logging and Recovery for Home-Based Software Distributed Shared Memory
The probability of failures in software distributed shared memory (SDSM) increases as the system size grows. This paper introduces a new, efficient message logging technique, call...
Angkul Kongmunvattana, Nian-Feng Tzeng
CISIS
2009
IEEE
16 years 1 months ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
CGO
2005
IEEE
15 years 12 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...