The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
This paper analyzes the impact of hardware multithreading support on the performance of distributed shared-memory DSM multiprocessors built out of heterogeneous, single-chip compu...
Renato J. O. Figueiredo, Jeffrey P. Bradford, Jos&...
Hyperlinks among webpages are very important information and are widely used for webpage clustering and webpage ranking. With the explosive growth in the number of webpages availab...
Hong Zhou, Yingcai Wu, Ming-Yuen Chan, Huamin Qu, ...
Minimum-error-rate training (MERT) is a bottleneck for current development in statistical machine translation because it is limited in the number of weights it can reliably optimi...
— We present a tool, PerfCenter, that takes as input the deployment, configuration, message flow and workload details of the hardware and software servers in an application hos...