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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 12 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
IEEEPACT
1998
IEEE
15 years 11 months ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
NOCS
2007
IEEE
16 years 1 months ago
Towards Open Network-on-Chip Benchmarks
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challe...
Cristian Grecu, André Ivanov, Partha Pratim...
CIDR
2007
144views Algorithms» more  CIDR 2007»
15 years 8 months ago
Cache-Oblivious Query Processing
We propose a radical approach to relational query processing that aims at automatically and consistently achieving a good performance on any memory hierarchy. We believe this auto...
Bingsheng He, Qiong Luo
CCGRID
2008
IEEE
16 years 1 months ago
Admission Control in a Computational Market
We propose, implement and evaluate three admission models for computational Grids. The models take the expected demand into account and offer a specific performance guarantee. Th...
Thomas Sandholm, Kevin Lai, Scott H. Clearwater