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HPCA
1999
IEEE
15 years 11 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
DAC
2008
ACM
16 years 8 months ago
Predictive design space exploration using genetically programmed response surfaces
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically programmed response surface...
Henry Cook, Kevin Skadron
EGPGV
2011
Springer
366views Visualization» more  EGPGV 2011»
14 years 10 months ago
GPU Algorithms for Diamond-based Multiresolution Terrain Processing
We present parallel algorithms for processing, extracting and rendering adaptively sampled regular terrain datasets represented as a multiresolution model defined by a super-squa...
M. Adil Yalçin, Kenneth Weiss, Leila De Flo...
CL
2007
Springer
15 years 7 months ago
A bulk-synchronous parallel process algebra
The CCS (Calculus of Communicating Systems) process algebra is a well-known formal model of synchronization and communication. It is used for the analysis of safety and liveness i...
Armelle Merlin, Gaétan Hains
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
15 years 9 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...