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VLSID
2002
IEEE
172views VLSI» more  VLSID 2002»
16 years 6 months ago
Improvement of ASIC Design Processes
With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this con...
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
WISE
2009
Springer
16 years 3 months ago
Formal Identification of Right-Grained Services for Service-Oriented Modeling
Identifying the right-grained services is important to lead the successful service orientation because it has a direct impact on two major goals: the composability of loosely-coupl...
Yukyong Kim, Kyung-Goo Doh
IWSOS
2007
Springer
16 years 15 days ago
Mercator: Self-organizing Geographic Connectivity Maps for Scalable Ad-Hoc Routing
Abstract. A fundamental problem of future networks is to get fully selforganized routing protocols with good scalability properties that produce good paths in a wide range of netwo...
Luis A. Hernando, Unai Arronategui
CIMCA
2006
IEEE
16 years 12 days ago
Timed-MPSG: A Formal Model for Real-Time Shop Floor Controller
The MPSG (Message-based Part State Graph) model has been developed for the execution portion of shop-floor controllers that operate in a distributed and hierarchical control envir...
Devinder Thapa, Jaeil Park, Gi-Nam Wang, Dongmin S...
ICSE
2001
IEEE-ACM
15 years 10 months ago
JMOCHA: A Model Checking Tool that Exploits Design Structure
Mocha is a model checker based on the theme of exploiting design modularity: instead of manipulating unstructured state-transition graphs, it supports the hierarchical modeling fra...
Rajeev Alur, Luca de Alfaro, Radu Grosu, Thomas A....