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DAC
2004
ACM
15 years 10 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
FPL
2006
Springer
140views Hardware» more  FPL 2006»
15 years 10 months ago
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
APCSAC
2003
IEEE
15 years 10 months ago
On Implementing High Level Concurrency in Java
Abstract. Increasingly threading has become an important architectural component of programming languages to support parallel programming. Previously we have proposed an elegant la...
G. Stewart Von Itzstein, Mark Jasiunas
CASES
2001
ACM
15 years 10 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu
SC
2000
ACM
15 years 10 months ago
High Performance Reactive Fluid Flow Simulations Using Adaptive Mesh Refinement on Thousands of Processors
We present simulations and performance results of nuclear burning fronts in supernovae on the largest domain and at the finest spatial resolution studied to date. These simulation...
A. C. Calder, Bruce C. Curtis, L. J. Dursi, Bruce ...
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