The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
This paper advocates that cache coherence protocols use a bandwidth adaptive approach to adjust to varied system configurations (e.g., number of processors) and workload behaviors...
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, ...
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the n...
The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm unfeasible for very la...