Sciweavers

21437 search results - page 4120 / 4288
» Hardware
Sort
View
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
16 years 3 days ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
HPCS
2005
IEEE
16 years 3 days ago
A Lightweight, Scalable Grid Computing Framework for Parallel Bioinformatics Applications
Abstract— In recent years our society has witnessed an unprecedented growth in computing power available to tackle important problems in science, engineering and medicine. For ex...
Hans De Sterck, Rob S. Markel, Rob Knight
ICEIS
2005
IEEE
16 years 2 days ago
Conditions for Interoperability
Abstract: Interoperability for information systems remains a challenge both at the semantic and organisational levels. The original three-level architecture for local databases nee...
B. Nick Rossiter, Michael A. Heather
ICPPW
2005
IEEE
16 years 2 days ago
Speculative Parallel Threading Architecture and Compilation
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
Xiao-Feng Li, Zhao-Hui Du, Chen Yang, Chu-Cheow Li...
ICSM
2005
IEEE
16 years 2 days ago
A Safe Regression Test Selection Technique for Database-Driven Applications
Regression testing is a widely-used method for checking whether modifications to software systems have adversely affected the overall functionality. This is potentially an expens...
David Willmor, Suzanne M. Embury
« Prev « First page 4120 / 4288 Last » Next »