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ERSA
2006
115views Hardware» more  ERSA 2006»
15 years 8 months ago
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation
Acoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo controller is its capability to hand...
Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven ...
ERSA
2006
119views Hardware» more  ERSA 2006»
15 years 8 months ago
Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment
Run-time assignment of a set of communicating tasks onto a heterogeneous multiprocessor system-on-chip (MPSoC) platform is a challenging task. Having FPGA fabric tiles in such MPS...
Vincent Nollet, Prabhat Avasare, Diederik Verkest,...
ERSA
2006
128views Hardware» more  ERSA 2006»
15 years 8 months ago
Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture
Mobile wireless communication systems become multi-mode systems. These future mobile systems employ multiple wireless communication standards, which are different by means of algor...
Gerard K. Rauwerda, Gerard J. M. Smit, Casper R. W...
ERSA
2006
197views Hardware» more  ERSA 2006»
15 years 8 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
ESANN
2006
15 years 8 months ago
FPGA implementation of an integrate-and-fire LEGION model for image segmentation
Abstract. Despite several previous studies, little progress has been made in building successful neural systems for image segmentation in digital hardware. Spiking neural networks ...
Bernard Girau, Cesar Torres-Huitzil
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