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DFT
2006
IEEE
148views VLSI» more  DFT 2006»
15 years 8 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
DAC
2005
ACM
15 years 8 months ago
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Finding all satisfying assignments of a propositional formula has many applications in the design of hardware and software. An approach to this problem augments a clause-recording...
HoonSang Jin, Fabio Somenzi
DAC
2005
ACM
15 years 8 months ago
A watermarking system for IP protection by a post layout incremental router
In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then ...
Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga
DAC
2005
ACM
15 years 8 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
DAC
2005
ACM
15 years 8 months ago
Sign bit reduction encoding for low power applications
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
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