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Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems
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Bren Mochocki, Razvan Racu, Rolf Ernst
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Noise margin analysis for dynamic logic circuits
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Suwen Yang, Mark R. Greenstreet
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M-trie: an efficient approach to on-chip logic minimization
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Seraj Ahmad, Rabi N. Mahapatra
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Design space exploration for a UMTS front-end exploiting analog platforms
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F. De Bernarclinis, S. Gambini, R. Vincis, F. Svel...
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A quantitative study and estimation models for extensible instructions in embedded processors
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Newton Cheung, Sri Parameswaran, Jörg Henkel
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