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Design and integration methods for a multi-threaded dual core 65nm Xeon® processor
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Raj Varada, Mysore Sriram, Kris Chou, James Guzzo
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Accelerating high-level bounded model checking
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Technology migration techniques for simplified layouts with restrictive design rules
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Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens
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Manoj Ampalam, Montek Singh
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Storage assignment during high-level synthesis for configurable architectures
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Wenrui Gong, Gang Wang, Ryan Kastner
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