We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
This paper presents an efficient hardware-accelerated method for novel view synthesis from a set of images or videos. Our method is based on the photo hull representation, which i...
A new ASIC capable of computing rank order "lters, weighted rank order "lters, standard erosion and dilation, soft erosion and dilation, order statistic soft erosion and...
We present a scalable volume rendering technique that exploits lossy compression and low-cost commodity hardware to permit highly interactive exploration of time-varying scalar vol...
Hardware accelerators are becoming a highly appealing approach to boost the raw performance as well as the price-performance and power-performance ratios of current clusters. In t...
Manuel Fogue, Francisco D. Igual, Enrique S. Quint...