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TVLSI
2008
140views more  TVLSI 2008»
15 years 6 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
CGF
2004
94views more  CGF 2004»
15 years 6 months ago
Hardware-Accelerated Rendering of Photo Hulls
This paper presents an efficient hardware-accelerated method for novel view synthesis from a set of images or videos. Our method is based on the photo hull representation, which i...
Ming Li, Marcus A. Magnor, Hans-Peter Seidel
PR
2000
106views more  PR 2000»
15 years 6 months ago
Non-linear image processing in hardware
A new ASIC capable of computing rank order "lters, weighted rank order "lters, standard erosion and dilation, soft erosion and dilation, order statistic soft erosion and...
Antonios Gasteratos, Ioannis Andreadis
TVCG
2002
156views more  TVCG 2002»
15 years 6 months ago
A Hardware-Assisted Scalable Solution for Interactive Volume Rendering of Time-Varying Data
We present a scalable volume rendering technique that exploits lossy compression and low-cost commodity hardware to permit highly interactive exploration of time-varying scalar vol...
Eric B. Lum, Kwan-Liu Ma, John Clyne
IEEEHPCS
2010
15 years 5 months ago
Retargeting PLAPACK to clusters with hardware accelerators
Hardware accelerators are becoming a highly appealing approach to boost the raw performance as well as the price-performance and power-performance ratios of current clusters. In t...
Manuel Fogue, Francisco D. Igual, Enrique S. Quint...