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IISWC
2008
IEEE
16 years 1 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
16 years 20 days ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
IEEEPACT
2006
IEEE
16 years 19 days ago
Hardware support for spin management in overcommitted virtual machines
Multiprocessor operating systems (OSs) pose several unique and conflicting challenges to System Virtual Machines (System VMs). For example, most existing system VMs resort to gan...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
DSN
2005
IEEE
16 years 6 days ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh
AADEBUG
2005
Springer
16 years 4 days ago
Code coverage testing using hardware performance monitoring support
Code coverage analysis, the process of finding code exercised by a particular set of test inputs, is an important component of software development and verification. Most tradit...
Alex Shye, Matthew Iyer, Vijay Janapa Reddi, Danie...