Abstract. As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call...
Josep Carmona, Jordi Cortadella, Victor Khomenko, ...
In this paper, we propose an effective bump mapping algorithm that utilizes the reference space with the polar coordinate system and also propose a new hardware architecture assoc...
S. G. Lee, W. C. Park, W. J. Lee, T. D. Han, S. B....
We show how a future graphics processor unit (GPU), enhanced with random read and write to video memory, can represent, refine and adjust complex meshes arising in modeling, simu...
A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulations experiments are design...
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...