This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
Synchronous programming languages have proved to be advantageous for designing software and hardware for embedded systems. Despite their clear semantics, their compilation is rema...
Existing software thread integration (STI) methods provide synchronous thread progress within integrated functions. For the remaining, non-integrated portions of the secondary (or...
Nagendra J. Kumar, Siddhartha Shivshankar, Alexand...
— This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs,...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...