421 search results - page 50 / 85 » Hardware efficient architectures for Eigenvalue computation |
154
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
183
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CODES
2006
IEEE
16 years 2 days ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
152
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SIGCOMM
2010
ACM
15 years 6 months ago
2010
ACM
Traditionally, in-network services like firewall, proxy, cache, and transcoders have been provided by dedicated hardware middleboxes. A recent trend has been to remove the middleb...
162
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ISCAS
2007
IEEE
16 years 9 days ago
2007
IEEE
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...
171
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VLSID
2001
IEEE
16 years 6 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...