Sciweavers

3902 search results - page 531 / 781
» Hardware Synthesis from C C Models
Sort
View
CC
2007
Springer
16 years 25 days ago
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung...
CODES
2006
IEEE
16 years 22 days ago
Bounded arbitration algorithm for QoS-supported on-chip communication
Time-critical multi-processor systems require guaranteed services in terms of throughput, bandwidth etc. in order to comply to hard real-time constraints. However, guaranteedservi...
Mohammad Abdullah Al Faruque, Gereon Weiss, Jö...
263
Voted
ISCAS
2005
IEEE
119views Hardware» more  ISCAS 2005»
16 years 7 days ago
Multi-plet two-channel perfect reconstruction filter banks
This paper proposes a new class of two-channel structural perfect reconstruction (PR) FIR filter banks (FBs) called the multi-plet FB. It generalizes structural PR FBs proposed by...
S. C. Chan, K. M. Tsui
SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
16 years 6 days ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
SIGMETRICS
2005
ACM
101views Hardware» more  SIGMETRICS 2005»
16 years 6 days ago
Fundamental bounds on the accuracy of network performance measurements
This paper considers the basic problem of “how accurate can we make Internet performance measurements”. The answer is somewhat counter-intuitive in that there are bounds on th...
Matthew Roughan