3902 search results - page 421 / 781 » Hardware Synthesis from C C Models |
168
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ASPDAC
2000
ACM
15 years 11 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
190
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ASYNC
1999
IEEE
15 years 11 months ago
1999
IEEE
The counterflow pipeline architecture [12] consists of two interacting pipelines in which data items flow in opposite directions. Interactions occur between two items when they me...
150
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ISCA
1999
IEEE
15 years 11 months ago
1999
IEEE
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
132
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ISPD
1998
ACM
15 years 11 months ago
1998
ACM
—The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this...
178
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MICRO
1997
IEEE
15 years 11 months ago
1997
IEEE
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...