3902 search results - page 417 / 781 » Hardware Synthesis from C C Models |
187
click to vote
DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
153
click to vote
GECCO
2006
Springer
15 years 10 months ago
2006
Springer
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
221
click to vote
SIGMETRICS
2012
ACM
13 years 9 months ago
2012
ACM
This paper presents a benchmarking suite that measures the performance of using sockets and eXtensible Markup Language remote procedure calls (XML-RPC) to exchange intra-node mess...
131
click to vote
ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
Abstract—Because of the today’s market demand for highperformance, high-density portable hand-held applications, electronic system design technology has shifted the focus from ...
147
click to vote
ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...