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ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
16 years 3 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
175
Voted
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
15 years 11 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
MICRO
1998
IEEE
111views Hardware» more  MICRO 1998»
15 years 11 months ago
Precise Register Allocation for Irregular Architectures
This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP registe...
Timothy Kong, Kent D. Wilken
CVPR
2012
IEEE
13 years 9 months ago
Top-down and bottom-up cues for scene text recognition
Scene text recognition has gained significant attention from the computer vision community in recent years. Recognizing such text is a challenging problem, even more so than the ...
Anand Mishra, Karteek Alahari, C. V. Jawahar
ACSAC
1999
IEEE
15 years 11 months ago
A Resource Access Decision Service for CORBA-Based Distributed Systems
Decoupling authorization logic from application logic allows applications with fine-grain access control requirements to be independent from a particular access control policy and...
Konstantin Beznosov, Yi Deng, Bob Blakley, C. Burt...