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HOTI
2005
IEEE
16 years 10 days ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
16 years 9 days ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
SIGMETRICS
2005
ACM
163views Hardware» more  SIGMETRICS 2005»
16 years 8 days ago
Smooth switching problem in buffered crossbar switches
Scalability considerations drive the switch fabric design to evolve from output queueing to input queueing and further to combined input and crosspoint queueing (CICQ). However, f...
Simin He, Shutao Sun, Wei Zhao, Yanfeng Zheng, Wen...
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
16 years 4 days ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
SIGMETRICS
2004
ACM
106views Hardware» more  SIGMETRICS 2004»
16 years 4 days ago
Quantifying trade-offs in resource allocation for VPNs
Virtual Private Networks (VPNs) feature notable characteristics in structure and traffic patterns that allow for efficient resource allocation. A strategy that exploits the underl...
Satish Raghunath, Shivkumar Kalyanaraman, K. K. Ra...