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DATE
2003
IEEE
87views Hardware» more  DATE 2003»
15 years 12 months ago
A Proposal for Transaction-Level Verification with Component Wrapper Language
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...
Koji Ara, Kei Suzuki
ISPD
1997
ACM
105views Hardware» more  ISPD 1997»
15 years 10 months ago
Regular layout generation of logically optimized datapaths
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
R. X. T. Nijssen, C. A. J. van Eijk
EUROPAR
1995
Springer
15 years 10 months ago
Bounds on Memory Bandwidth in Streamed Computations
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance ga...
Sally A. McKee, William A. Wulf, Trevor C. Landon
IACR
2011
192views more  IACR 2011»
14 years 6 months ago
The Hummingbird-2 Lightweight Authenticated Encryption Algorithm
Hummingbird-2 is an encryption algorithm with a 128-bit secret key and a 64-bit initialization vector. Hummingbird-2 optionally produces an authentication tag for each message proc...
Daniel Engels, Markku-Juhani O. Saarinen, Peter Sc...
DDECS
2009
IEEE
95views Hardware» more  DDECS 2009»
16 years 1 months ago
Self-timed full adder designs based on hybrid input encoding
—Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are desc...
Padnamabhan Balasubramanian, D. A. Edwards, C. Bre...