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» Hardware Synthesis from C C Models
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MTDT
2003
IEEE
164views Hardware» more  MTDT 2003»
15 years 12 months ago
Applying Defect-Based Test to Embedded Memories in a COT Model
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
Robert C. Aitken
LION
2009
Springer
135views Optimization» more  LION 2009»
16 years 1 months ago
Neural Network Pairwise Interaction Fields for Protein Model Quality Assessment
We present a new knowledge-based Model Quality Assessment Program (MQAP) at the residue level which evaluates single protein structure models. We use a tree representation of the ...
Alberto J. M. Martin, Alessandro Vullo, Gianluca P...
NOCS
2008
IEEE
16 years 1 months ago
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
Bart Vermeulen, Kees Goossens, Siddharth Umrani
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
16 years 28 days ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
BIRTHDAY
2005
Springer
16 years 5 days ago
Model Theory for Process Algebra
We present a first-order extension of the algebraic theory about processes known as ACP and its main models. Useful predicates on processes, such as deadlock freedom and determini...
Jan A. Bergstra, C. A. Middelburg