3902 search results - page 269 / 781 » Hardware Synthesis from C C Models |
154
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DATE
2007
IEEE
16 years 29 days ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
163
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DATE
2007
IEEE
16 years 29 days ago
2007
IEEE
Customizable processors are being used increasingly often in SoC designs. During the past few years, they have proven to be a good way to solve the conflicting flexibility and p...
160
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ECBS
2007
IEEE
16 years 29 days ago
2007
IEEE
Automated diagnosis of errors detected during software testing can improve the efficiency of the debugging process, and can thus help to make software more reliable. In this pape...
166
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ISQED
2005
IEEE
16 years 6 days ago
2005
IEEE
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
140
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ISQED
2003
IEEE
15 years 12 months ago
2003
IEEE
An intermediate solution between conventional printed circuit board technology and wafer level packaging, WLP, is to fabricate interconnection circuits and flip chip assembly stru...