3902 search results - page 266 / 781 » Hardware Synthesis from C C Models |
155
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ISQED
2003
IEEE
15 years 12 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
154
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ISQED
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper presents an electrical and thermal performance analysis of System-in-a-Package (SiP) memory/logic implementation platform based on ChipLaminate-Chip (CLC) technology. I...
154
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EH
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper discusses approaches to cooperative coevolution of form and function for autonomous vehicles, specifically evolving morphology and control for an autonomous micro air v...
148
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ICCAD
1996
IEEE
15 years 10 months ago
1996
IEEE
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
151
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
－ We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...