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ISCAS
2006
IEEE
92views Hardware» more  ISCAS 2006»
16 years 13 days ago
Time-sliding suboptimal regulation of bilinear interconnected systems
— This paper focuses on the suboptimal regulation of multivariable discrete-time bilinear systems consisting of interconnected bilinear subsystems with respect to a linear quadra...
Manuel de la Sen, Aitor J. Garrido, J. C. Soto, Os...
DAC
2004
ACM
16 years 7 months ago
Multiple constant multiplication by time-multiplexed mapping of addition chains
An important primitive in the hardware implementations of linear DSP transforms is a circuit that can multiply an input value by one of several different preset constants. We prop...
James C. Hoe, Markus Püschel, Peter Tummeltsh...
SAC
2006
ACM
16 years 11 days ago
A concurrent reactive Esterel processor based on multi-threading
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...
Xin Li, Reinhard von Hanxleden
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 12 months ago
FPGA PLB Evaluation using Quantified Boolean Satisfiability
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
ISQED
2003
IEEE
119views Hardware» more  ISQED 2003»
15 years 11 months ago
System and Framework for QA of Process Design Kits
In this paper, we evaluate the dependencies between tools, data and environment in process design kits, and present a framework for systematically analyzing the quality of the des...
M. C. Scott, M. O. Peralta, Jo Dale Carothers