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IOLTS
2009
IEEE
124views Hardware» more  IOLTS 2009»
16 years 1 months ago
On-line characterization and reconfiguration for single event upset variations
The amount of physical variation among electronic components on a die is increasing rapidly. There is a need for a better understanding of variations in transient fault susceptibil...
Kenneth M. Zick, John P. Hayes
DATE
2007
IEEE
124views Hardware» more  DATE 2007»
16 years 1 months ago
Worst-case design and margin for embedded SRAM
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
Robert C. Aitken, Sachin Idgunji
DATE
2003
IEEE
93views Hardware» more  DATE 2003»
15 years 12 months ago
Comparison of Test Pattern Decompression Techniques
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...
Ondrej Novák
ASYNC
2002
IEEE
150views Hardware» more  ASYNC 2002»
15 years 11 months ago
Clock Synchronization through Handshake Signalling
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not...
Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters,...
FMCAD
2008
Springer
15 years 8 months ago
BackSpace: Formal Analysis for Post-Silicon Debug
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steve...