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DATE
1998
IEEE
74views Hardware» more  DATE 1998»
15 years 11 months ago
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
Michael S. Hsiao, Srimat T. Chakradhar
FUIN
2006
160views more  FUIN 2006»
15 years 6 months ago
Behavioral Pattern Identification Through Rough Set Modeling
This paper introduces an approach to behavioral pattern identification as a part of a study of temporal patterns in complex dynamical systems. Rough set theory introduced by Zdzisl...
Jan G. Bazan
QEST
2006
IEEE
16 years 24 days ago
Modeling Fiber Delay Loops in an All Optical Switch
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
15 years 11 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
16 years 1 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy