4074 search results - page 438 / 815 » Hardware Modelling and Simulation Using an Object-Oriented M... |
161
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
152
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ATS
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper addresses the problem of locating the stuckopen faults in a manufactured IC with scan flip-flops. Unlike most previous methods that only aim at identifying the faulty s...
149
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
147
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ISCAS
1999
IEEE
15 years 11 months ago
1999
IEEE
An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in the conversion time, ...
170
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DATE
2005
IEEE
16 years 12 days ago
2005
IEEE
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...