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CHARME
2001
Springer
92views Hardware» more  CHARME 2001»
15 years 10 months ago
Induction-Oriented Formal Verification in Symmetric Interconnection Networks
The framework of this paper is the formal specification and proof of applications distributed on symmetric interconnection networks, e.g. the torus or the hypercube. The algorithms...
Eric Gascard, Laurence Pierre
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
15 years 11 months ago
Instruction fetch deferral using static slack
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
Gregory A. Muthler, David Crowe, Sanjay J. Patel, ...
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
15 years 11 months ago
FunState - an internal design representation for codesign
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components a...
Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Ro...
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
16 years 7 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
CHARME
2005
Springer
143views Hardware» more  CHARME 2005»
16 years 11 days ago
Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning
Abstract. We propose a new saturation-based symbolic state-space generation algorithm for finite discrete-state systems. Based on the structure of the high-level model specificat...
Gianfranco Ciardo, Andy Jinqing Yu