Sciweavers

4074 search results - page 406 / 815
» Hardware Modelling and Simulation Using an Object-Oriented M...
Sort
View
QEST
2007
IEEE
16 years 1 months ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
GECCO
2004
Springer
116views Optimization» more  GECCO 2004»
16 years 6 days ago
Reducing Fitness Evaluations Using Clustering Techniques and Neural Network Ensembles
Abstract. In many real-world applications of evolutionary computation, it is essential to reduce the number of fitness evaluations. To this end, computationally efficient models c...
Yaochu Jin, Bernhard Sendhoff
DAC
2005
ACM
15 years 8 months ago
Piece-wise approximations of RLCK circuit responses using moment matching
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
169
Voted
SBACPAD
2003
IEEE
102views Hardware» more  SBACPAD 2003»
16 years 2 days ago
Performance Analysis of DECK Collective Communication Service
Collective communication is very useful for parallel applications, especially those in which matrix and vector data structures need to be manipulated by a group of processes. This...
Rafael Ennes Silva, Delcino Picinin, Marcos E. Bar...
EUROCAST
2009
Springer
116views Hardware» more  EUROCAST 2009»
15 years 10 months ago
Complete Sets of Hamiltonian Circuits for Classification of Documents
The calculation of Hamiltonian Circuits is an NP-complete task. This paper uses slightly modified complete sets of Hamiltonian circuits for the classification of documents. The sol...
Bernd Steinbach, Christian Posthoff