We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
We describe a formal verification of a recent concurrent list-based set algorithm due to Heller et al. The algorithm is optimistic: the add and remove operations traverse the list ...
Robert Colvin, Lindsay Groves, Victor Luchangco, M...
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
This paper presents an energy-ecient biped walking method that has been implemented in a low-cost humanoid platform, PINO, for various research purposes. For biped walking robots ...
Fuminori Yamasaki, Ken Endo, Minoru Asada, Hiroaki...