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DATE
2006
IEEE
135views Hardware» more  DATE 2006»
16 years 24 days ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
172
Voted
CAV
2006
Springer
141views Hardware» more  CAV 2006»
15 years 10 months ago
Formal Verification of a Lazy Concurrent List-Based Set Algorithm
We describe a formal verification of a recent concurrent list-based set algorithm due to Heller et al. The algorithm is optimistic: the add and remove operations traverse the list ...
Robert Colvin, Lindsay Groves, Victor Luchangco, M...
FPL
2009
Springer
172views Hardware» more  FPL 2009»
15 years 11 months ago
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
Nachiket Kapre, André DeHon
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
15 years 11 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
ROBOCUP
2001
Springer
121views Robotics» more  ROBOCUP 2001»
15 years 11 months ago
A Control Method for Humanoid Biped Walking with Limited Torque
This paper presents an energy-ecient biped walking method that has been implemented in a low-cost humanoid platform, PINO, for various research purposes. For biped walking robots ...
Fuminori Yamasaki, Ken Endo, Minoru Asada, Hiroaki...