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ARCS
2004
Springer
16 years 4 days ago
Modelling Cryptonite - On the Design of a Programmable High-Performance Crypto Processor
: Cryptographic algorithms – even when designed for easy implementability on general purpose architectures – still show a huge performance gap between implementations in softwa...
Rainer Buchty
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
16 years 3 months ago
A Novel Low-Power Scan Design Technique Using Supply Gating
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukh...
ISCAS
2007
IEEE
148views Hardware» more  ISCAS 2007»
16 years 1 months ago
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter
— Mismatches between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) cause undesirable distortions in the output spectrum. To reduce t...
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
16 years 3 hour ago
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
15 years 10 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah