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ICCAD
2009
IEEE
113views Hardware» more  ICCAD 2009»
15 years 4 months ago
A performance analytical model for Network-on-Chip with constant service time routers
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
Nikita Nikitin, Jordi Cortadella
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
15 years 8 months ago
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho S...
ICECCS
2006
IEEE
140views Hardware» more  ICECCS 2006»
16 years 21 days ago
Inference of Design Pattern Instances in UML models via Logic Programming
This paper formalizes the notion of a design model structurally conforming to a design pattern by representing the model as a logic program whilst the pattern as a query. The conf...
Dae-Kyoo Kim, Lunjin Lu
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
15 years 11 months ago
A Discrete-Time Battery Model for High-Level Power Estimation
In this paper, we introduce a discrete-time model for the complete power supply sub-system that closely approximates the behavior of its circuit-level (i.e., HSpice), continuous-t...
Luca Benini, Giuliano Castelli, Alberto Macii, Enr...
ACSD
2004
IEEE
95views Hardware» more  ACSD 2004»
15 years 10 months ago
Guided Model Checking with a Bayesian Meta-heuristic
Abstract. This paper presents a formal verification algorithm for finding errors in models of complex concurrent systems. The algorithm improves explicit guided model checking by a...
Kevin D. Seppi, Michael Jones, Peter Lamborn