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CHES
2006
Springer
146views Cryptology» more  CHES 2006»
15 years 10 months ago
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
16 years 3 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
PARELEC
2000
IEEE
15 years 10 months ago
Parallel Computing Environments and Methods
Recent advances in high-speed networks, rapid improvements in microprocessor design, and availability of highly performing clustering software implementations enables cost-effecti...
Ghassan Fadlallah, Michel Lavoie, Louis-A. Dessain...
ASPDAC
2005
ACM
153views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Design of clocked circuits using UML
– Clocking is an essential component of any embedded system design. However, traditional design techniques are either short of clocking support or too complex for users. The Unif...
Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh ...
DAC
2002
ACM
16 years 7 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...