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ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
16 years 2 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
ISQED
2007
IEEE
197views Hardware» more  ISQED 2007»
16 years 4 days ago
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
Toshinori Sato, Yuji Kunitake
ISPD
2006
ACM
103views Hardware» more  ISPD 2006»
15 years 12 months ago
High accurate pattern based precondition method for extremely large power/ground grid analysis
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...
ISCAS
2003
IEEE
168views Hardware» more  ISCAS 2003»
15 years 11 months ago
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder
MPEG-4 Fine Granularity Scalability (FGS) provides bandwidth adaptation and error resilience features for streaming applications. In this paper. by estimating the required computa...
Chih-Wei Hsu, Yung-Chi Chang, Wei-Min Chao, Liang-...
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
15 years 11 months ago
Hysteresis of Intrinsic IDDQ Currents
: Empirical analyses of the IDDQ signatures of 0.18 µm devices indicate that IDDQ currents exhibit hysteresis. A newly proposed test method, SPIRIT (Single Pattern Iteration IDDQ ...
Yukio Okuda, Nobuyuki Furukawa