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ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
15 years 11 months ago
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
15 years 9 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
WDAG
2007
Springer
73views Algorithms» more  WDAG 2007»
15 years 12 months ago
On Self-stabilizing Synchronous Actions Despite Byzantine Attacks
Consider a distributed network of n nodes that is connected to a global source of “beats”. All nodes receive the “beats” simultaneously, and operate in lock-step. A scheme ...
Danny Dolev, Ezra N. Hoch
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 10 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
IPSN
2010
Springer
16 years 21 days ago
High-resolution, low-power time synchronization an oxymoron no more
We present Virtual High-resolution Time (VHT), a powerproportional time-keeping service that offers a baseline power draw of a low-speed clock (e.g. 32 kHz crystal), but provides...
Thomas Schmid, Prabal Dutta, Mani B. Srivastava