6110 search results - page 969 / 1222 » Graceful Network Operations |
168
click to vote
DSN
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
174
Voted
DSN
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper presents a scalable mechanism, Fast Routing Table Recovery (FRTR), for detecting and correcting route inconsistencies between neighboring BGP routers. The large size of...
221
click to vote
FPL
2006
Springer
15 years 10 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
184
click to vote
CLUSTER
2001
IEEE
15 years 10 months ago
2001
IEEE
The Virtual Interface Architecture (VIA) is an industry standard user-level communication architecture for system area networks. The VIA provides a protected, directlyaccessible i...
164
click to vote
CL
2000
Springer
15 years 10 months ago
2000
Springer
Abstract. We propose an extension of concurrent constraint programming with primitives for process migration within a hierarchical network, and we study its semantics. To this purp...