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HOTI
2005
IEEE
16 years 11 days ago
Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication
Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bo...
Robert J. Drost, Craig Forrest, Bruce Guenin, Ron ...
HOTI
2005
IEEE
16 years 11 days ago
Addressing Queuing Bottlenecks at High Speeds
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 11 days ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
ICCV
2005
IEEE
16 years 11 days ago
Non-Negative Lighting and Specular Object Recognition
Recognition of specular objects is particularly difficult because their appearance is much more sensitive to lighting changes than that of Lambertian objects. We consider an appr...
Sameer Shirdhonkar, David W. Jacobs
ICDCSW
2005
IEEE
16 years 11 days ago
Defending against Sybil Attacks in Sensor Networks
Sybil attack is a harmful threat to sensor networks, in which a malicious node illegally forges an unbounded number of identities to defeat redundancy mechanisms. Digital certifi...
Qinghua Zhang, Pan Wang, Douglas S. Reeves, Peng N...
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