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» Geometry of synthesis: a structured approach to VLSI design
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ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
15 years 9 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
SIGGRAPH
1996
ACM
15 years 10 months ago
Modeling and Rendering of Metallic Patinas
An important component that has been missing from image synthesis is the effect of weathering. In this paper, we present an approach for the modeling and rendering of one type of ...
Julie Dorsey, Pat Hanrahan
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
15 years 9 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
149
Voted
GLVLSI
2007
IEEE
111views VLSI» more  GLVLSI 2007»
16 years 12 days ago
Probabilistic gate-level power estimation using a novel waveform set method
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Ein...
194
Voted
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
16 years 6 months ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...