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» Geometry of synthesis: a structured approach to VLSI design
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CODES
2004
IEEE
15 years 9 months ago
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
Hyunuk Jung, Soonhoi Ha
VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
15 years 10 months ago
A New Methodology for Concurrent Technology Development and Cell Library Optimization
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, P...
171
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LPNMR
2009
Springer
16 years 19 days ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
ISCAS
1999
IEEE
114views Hardware» more  ISCAS 1999»
15 years 10 months ago
Nonuniformly offset polyphase synthesis of a bandpass signal from complex-envelope samples
In this paper we consider the synthesis of a bandpass signal from complex-envelope samples using a polyphase conversion structure based on periodically nonuniform output samples. ...
D. Scholnik, J. O. Coleman
DAC
2003
ACM
16 years 7 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...