A machine_independent abstract program representation is presented that is twice as compact as machine code for a CISC processor. It forms the basis of an implementation, in which ...
We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their ion in a system on chip. We abstract the communication behaviour of the data flow IP so a...
Following the simple Programmable Logic Device (SPLD) and Field Programmable Gate Array (FPGA) generations a third generation of programmable logic technologies is now reaching the...
We present a variant of the Standard ML module system rameterized abstract types (i.e. functors returning generative types) map provably equal arguments to compattract types, inst...
We show that the number of vertices of a given degree k in several kinds of series-parallel labelled graphs of size n satisfy a central limit theorem with mean and variance proport...