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ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
15 years 11 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
3DPVT
2002
IEEE
169views Visualization» more  3DPVT 2002»
15 years 11 months ago
Compression of Isosurfaces for Structured Volumes with Context Modelling
In many applications surfaces with a large number of primitives occur. Geometry compression reduces storage space and transmission time for such models. A special case is given by...
Dietmar Saupe, Jens-Peer Kuska
ICRA
2002
IEEE
120views Robotics» more  ICRA 2002»
15 years 11 months ago
Workspace Optimization of 3-UPU Parallel Platforms with Joint Constraints
In this paper the workspace optimization of translational 3-UPU parallel platforms with prismatic and universal joint constraints is performed. The workspace is parameterized usin...
Mircea Badescu, Jeremy Morman, Constantinos Mavroi...
INFOCOM
2002
IEEE
15 years 11 months ago
Travelling Miser Problem
— Various monitoring and performance evaluation tools generate considerable amount of low priority traffic. This information is not always needed in real time, and thus could of...
Yuval Shavitt, David Breitgand, Danny Raz
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
15 years 11 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti