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DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 10 months ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
GECCO
2006
Springer
206views Optimization» more  GECCO 2006»
15 years 10 months ago
A dynamically constrained genetic algorithm for hardware-software partitioning
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
Pierre-André Mudry, Guillaume Zufferey, Gia...
PLDI
1995
ACM
15 years 10 months ago
A Type-Based Compiler for Standard ML
Compile-time type information should be valuable in efficient compilation of statically typed functional languages such as Standard ML. But how should type-directed compilation w...
Zhong Shao, Andrew W. Appel
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 10 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
ESA
2008
Springer
115views Algorithms» more  ESA 2008»
15 years 8 months ago
A New Approach to Exact Crossing Minimization
The crossing number problem is to find the smallest number of edge crossings necessary when drawing a graph into the plane. Eventhough the problem is NP-hard, we are interested in ...
Markus Chimani, Petra Mutzel, Immanuel M. Bomze