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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 12 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ISLPED
2003
ACM
129views Hardware» more  ISLPED 2003»
15 years 12 months ago
A critical analysis of application-adaptive multiple clock processors
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
Emil Talpes, Diana Marculescu
ISLPED
2003
ACM
152views Hardware» more  ISLPED 2003»
15 years 12 months ago
An MTCMOS design methodology and its application to mobile computing
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are use...
Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae P...
ISPD
2003
ACM
121views Hardware» more  ISPD 2003»
15 years 12 months ago
Optimality, scalability and stability study of partitioning and placement algorithms
This paper studies the optimality, scalability and stability of stateof-the-art partitioning and placement algorithms. We present algorithms to construct two classes of benchmarks...
Jason Cong, Michail Romesis, Min Xie
ISPD
2003
ACM
79views Hardware» more  ISPD 2003»
15 years 12 months ago
Floorplanning of pipelined array modules using sequence pairs
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
Matthew Moe, Herman Schmit
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